| 沒有 | 符號 | | | | 功能 |
| 1 | GND | | | | 電源接地 |
| 2 | LEDK | | | | LED陰極 |
| 3 | 發光二極管 | | | | LED陽極 |
| 4 | GND | | | | 電源接地 |
| 5 | 時鐘脈衝 | | | | MIPI-DSI clock lane positive-end input pin |
| 6 | 時鐘 | | | | MIPI-DSI clock lane negative-end input pin |
| 7 | GND | | | | 電源接地 |
| 8 | MIPI_D0P | | | | MIPI-DSI data lane positive-end input pin. (Data lane 0 positive polarity)) |
| 9 | MIPI_D0N | | | | MIPI-DSI data lane negative-end input pin.(Data lane 0 negative polarity) |
| 10 | GND | | | | 電源接地 |
| 11 | IM2 | IM1 | IMO | MPU Interface Mode | Data pin |
| IM1 | 0 | 0 | 0 | 3-line 9bit serial I/F | SDA: in/out |
| 0 | 0 | 1 | MIPI_3-line 9bit serial I/F | SDA: in/out DP/DN |
| 12 | 0 | 1 | 0 | 2 data lane serial I/F | SDA1: in/out SDA2: in |
| IM2 | 0 | 1 | 1 | QSPI I/F | SDA[3:0]: in/out |
| 1 | 0 | 0 | RGB_3-line 9bit serial I/F | SDA: in/out DB[5:0]: out |
| 13 | 1 | 0 | 1 | RGB_4-line 8bit serial I/F | SDA: in/out DB[5:0]: out |
| IM3 | 1 | 1 | 0 | 4-line 8bit serial I/F | SDA: in/out |
| 1 | 1 | 1 | 80-8bit parallel I/F | DB[7:0] |
| 14 | IOVCC | | | | Power Supply for logic, VDDIO=1.65V~3.3V. |
| 15 | 電源電壓(3.3V) | | | | Power Supply for Analog, VDD=2.4V~3.3V |
| 16 | VS | | | | Vertical (Frame) synchronizing input signal in RGB interface |
| 17 | HS | | | | Horizontal (Line) synchronizing input signal in RGB interface |
| 18 | TE | | | | Tearing effect output pin to synchronize MCU to frame writing. This pin is low |
| | | when it is not activated. If not used, please open it |
| 19 | RESET | | | | This signal low will reset the device and must be applied to properly initialize the |
| | | chip. Signal is low active |
| 20 | GND | | | | 電源接地 |
| 21 | D7 | | | | Data signal for DBI Type B mode |
| 22 | D6 | | | | Data signal for DBI Type B mode |
| 23 | D5 | | | | Data signal for DBI Type B mode |
| 24 | D4 | | | | Data signal for DBI Type B mode |
| 25 | D3(SDA3) | | | | Data signal for DBI Type B mode |
| 26 | D2(SDA2) | | | | Data signal for DBI Type B mode |
| 27 | D1(SDA1) | | | | Data signal for DBI Type B mode |
| 28 | D0(SDA0) | | | | Data signal for DBI Type B mode |
| 29 | CS | | | | Chip select pin of DBI Type B mode. Low active. |
| 30 | RD(SCL) | | | | Read Control pulse H duration |
| 31 | WR | | | | Write enable in MCU parallel interface |
| 32 | DCX | | | | Display data/command selection pin in parallel interface |
| 33 | GND | | | | 電源接地 |
| 34 | TP_SCL | | | | TP clock |
| 35 | TP_SDA | | | | TP data input |
| 36 | TP_RST | | | | TP Reset pin |
| 37 | TP_INT | | | | TP Communication interrupt for |
| 38 | TP_VCC | | | | TP POWER SUPPLY |
| 39 | GND | | | | 電源接地 |